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Frequency-to-Voltage Converter Based Dual-Loop PLL with Variable Phase Locking Capability
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  • Z Saifullah,
  • Paul Furth,
  • SriHarsh Pakala,
  • Alejandro Roman-Leora
Z Saifullah
New Mexico State University

Corresponding Author:[email protected]

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Paul Furth
New Mexico State University
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SriHarsh Pakala
New Mexico State University
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Alejandro Roman-Leora
Universidad Autonoma de Aguascalientes, Electronic Systems Department, Mexico
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A novel frequency-to-voltage converter (FVC) based phase-locked loop (PLL) is proposed to overcome the inability of an FVC-based frequency-locked loop (FLL) to lock phase. The proposed dual-loop PLL adds variable phase-locking capability, such that the phase locking angle can vary from 0o – 360o. The additional variable phase-locking can be applied in data communication in the form of phase modulation. The design is targeted for a 0.5-µm CMOS process. The proposed design generates a 480MHz clock from a reference clock of 15MHz. In simulation, the proposed PLL locks within 3.56 µs while consuming 1.61 mW of power.
13 Sep 2022Submitted to Electronics Letters
14 Sep 2022Submission Checks Completed
14 Sep 2022Assigned to Editor
14 Sep 2022Reviewer(s) Assigned
26 Sep 2022Review(s) Completed, Editorial Evaluation Pending
28 Sep 2022Editorial Decision: Revise Minor
06 Oct 20221st Revision Received
06 Oct 2022Submission Checks Completed
06 Oct 2022Assigned to Editor
06 Oct 2022Review(s) Completed, Editorial Evaluation Pending
07 Oct 2022Editorial Decision: Accept