(b) (c)
Fig. 7. (a) The proposed
clock pulse generator; (b) The proposed data branch sharing level
converting flip-flop based on conditional charging (DBS-LCFFCC); (c) The
proposed data branch sharing level converting flip-flop based on
precharging (DBS-LCFFP).
Fig. 7(b) shows the proposed data branch sharing level converting
flip-flop based on conditional charging (DBS-LCFFCC). The gates of
transistors P4 and N2 are controlled by the input signal D. Therefore,
the internal dynamic node X charge to ”1” only when the input signal D
is ”0”, at which time transistor P5 turns off. When the pulse signal
arrives, transistor N4 turns on, and the output node Q discharges to ”0”
through transistor N4. When the input signal D is ”1” and the pulse
signal arrives, transistor N4 turns on, and the output node Q can charge
to ”1” through N4. In addition, the internal dynamic node X discharge to
”0” as transistor P4 turns off and transistors N2 and N3 turn on. At
this time, transistor P5 turns on and the output node Q can charge to
”1” via P5. The charging and discharging paths of the output node Q are
composed of a single transistor N4, which realizes the data branch
sharing, reducing the number of transistors and further decreasing the
delay of the circuit.
Fig. 7(c) illustrates the proposed data branch sharing level-converting
flip-flop based on precharging (DBS-LCFFP). In contrast to the
DBS-LCFFCC, the DBS-LCFFP has the gate of the pull-up network transistor
P6 directly grounded for precharging the dynamic node X. As a result,
when the input signal D changes from ”1” to ”0”, the DBS-LCFFP does not
need to turn on the pull-up network transistor P4 before charging the
dynamic node X, which reduces the delay of the circuit. However, when
the input signal D is ”1” and the pulse signal arrives, the DBS-LCFFP
generates additional short circuit power consumption due to a short
circuit branch consisting of transistors P6, N5, and N6, which is not
present in the DBS-LCFFCC. This is because the DBS-LCFFCC uses the
conditional charging technique that avoids generating short circuit
power. Therefore, the DBS-LCFFCC has lower power consumption, while the
DBS-LCFFP has lower delay.
Simulation Results and Comparisons
The proposed LCFFs are simulated by HSPICE using PTM 32nm process
technology. The simulation experiment employs two supply voltages, among
which high supply voltage is 1.2V, and the low supply voltage is 0.8V.
The temperature is set to 25℃, the clock frequency is 125MHz, and the
output load is a 10fF capacitor. Fig. 8 shows the simulation waveforms
of the proposed LCFFs. Among them, the input signal D and the clock
signal CLK employ a low supply voltage (0.8V). Q1 is the output signal
of DBS-LCFFCC while Q2 is the output signal of DBS-LCFFP. We can observe
from Fig. 8 that when the pulse signal is ”0”, the output signals Q1 and
Q2 of the two LCFFs remain unchanged. When the pulse signal is ”1”, Q1
and Q2 collect the input signal D. Therefore, the proposed two LCFFs
have the correct logic function.