(a) (b)
Fig. 4. (a) Clock pulse generator; (b) Level converting
flip-flop based on pass-transistor logic (LCFFBPT).
Fig. 5 shows another proposed static level converting flip-flop (SLCFF)
[12]. The SLCFF uses a small keeper transistor MP3 to prevent node X
from becoming floated if the input signal D remains high during the
presence of the pulse. Transistor MP1 is controlled by the input signal
D. Node X remains low as long as the input signal D is high. However,
this approach introduces a significant delay, even though it eliminates
redundant switching activity at node X.
A novel double edge triggered level converter flip-flop (nDE-LCFF)
[13] is shown in Fig. 6, which uses conditional data mapping
technique to decrease redundant power consumption. However, the pulse
generator in nDE-LCFF generates narrow pulses through transistors N1 and
N2 on the rising edge of the clockand through transistor P1 on the
falling edge, resulting in an asymmetry between the two pulses that may
affect the circuit’s stability. In Additionally, the pulse signal
generator consumes relatively high power due to the use of large-sized
transistors.